module ext_bench;

    reg [10:0]  immd;
    reg [2:0]   mode;
    wire [15:0] immd16;

    ext U0 (
            .immd(immd),
            .mode(mode),
            .immd16(immd16)
           );

    integer k;
    initial
    begin
        immd = 11'b11010010110;
        for (k=0; k<=6; k=k+1)
            #5  mode = k;
        #10 $finish;
    end

    always @(mode)
    begin   
        #1;
        $display("mode=%b immd=%b immd16=%b",mode,immd,immd16);
    end
endmodule
